Method to improve the jitter of high frequency phase locked loop

Details Method to improve the jitter of high frequency phase locked loop Method to improve the jitter of high frequency phase locked loop

1998-03-06

2000-08-29

Kim, W. Chris

Dynamic magnetic information storage or retrieval

General processing of a digital signal

Data clocking

G11B 509

Patent

active

061117129

ABSTRACT:
A system and method is provided to improve the jitter performance of high frequency synthesizers used in read/write channel circuits. The frequency synthesizer is implemented with multiple phase locked loops arranged in a cascaded fashion to increase the update rates at which the cascaded loops operate at for a given frequency resolution of the synthesizer. The cascaded or staged phase locked loops may be utilized for generating read, write, and servo clocks for a read/write channel circuit. The cascaded phase locked loops may also be arranged such that one or more stages are shared to generate the read, write or servo clocks.

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