Microcomputer with built in debugging capability

Details Microcomputer with built in debugging capability Microcomputer with built in debugging capability

1995-03-29

1996-10-15

Beausoliel, Jr., Robert W.

Excavating

371 226, G01R 3128

Patent

active

055663001

ABSTRACT:
A debug instruction program is executed to enable a latch contents setting register to select the address of a specified part of a memory to be monitored. The selected address is given to a latch timing controller 18, and the internal state of the specified part of memory is supplied to a display contents latch unit according to information from an address bus and a bus timing control signal. The display contents latch unit latches the internal state and supplies it to a display device so that the internal state of memory can be identified and debugged.

REFERENCES:
patent: 4079449 (1978-03-01), Mercurio et al.
patent: 4386410 (1983-05-01), Pandya et al.
patent: 4639721 (1987-01-01), Eto et al.
patent: 4646077 (1987-02-01), Culley
patent: 4744084 (1988-05-01), Beck et al.
patent: 4792918 (1988-12-01), Hirase et al.
patent: 5072411 (1991-12-01), Yamaki

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