Vector multiprocessor system which individually indicates the da

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364247, 3642281, 364229, 3642468, 364DIG1, 364736, G06F 1516

Patent

active

051094991

ABSTRACT:
At least one common vector register capable of being accessed from a plurality of vector processors constituting the multiprocessor is provided in order to transfer vector data among the vector processors at a high speed. The common vector register includes data fields each holding the value of vector data, access control sections provided corresponding to the respective data fields and showing the status of data access from the vector processor for synchronization of data sending and receiving, when the vector data is transferred among the different vector processors through the common vector register, and an access right section used for managing the number of the vector processor which is allowed to access the common vector register.

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PCT/US82/01297, Oct. 5, 1981, Interface Mechanism Between Host Processor and Peripheral Controlling Processor.
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CRAY-1, the CRAY X-MP, the CRAY-2 and Beyond the Supercomputers of CRAY Research, J. Thompson, pp. 69-81.

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