Semiconductor memory device having stacked capacitor cells

Details Semiconductor memory device having stacked capacitor cells Semiconductor memory device having stacked capacitor cells

1990-02-05

1992-08-18

Hille, Rolf

357 45, 357 51, H01L 2968, H01L 2710, H01L 2702

Patent

active

051403897

ABSTRACT:
A semiconductor memory device having STC cells wherein the major portions of active regions consisting of channel-forming portions are inclined at an angle of 45 degrees with respect to word lines and bit lines that meet at right angles with each other, thereby enabling the storage capacitor portions to be arranged very densely and a sufficiently large capacitance to be maintained with very small cell areas. Since the storage capacitor portions are formed even on the bit lines, the bit lines are shielded, so that the capacitance decreases between the bit lines and, hence, the memory array noise decreases. It is also possible to design the charge storage capacitor portion so that a part thereof is in the form of a wall substantially vertical to the substrate in order to increase the capacitance.

REFERENCES:
patent: 4651183 (1987-03-01), Lange et al.
patent: 4742018 (1988-03-01), Kimura et al.
patent: 4910566 (1990-03-01), Ema

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