Vertical metal-oxide semiconductor devices

Details Vertical metal-oxide semiconductor devices Vertical metal-oxide semiconductor devices

1991-03-22

1992-08-18

Wojciechowicz, Edward J.

357 237, 357 41, 357 46, 357 55, H01L 2910

Patent

active

051403889

ABSTRACT:
A vertical CMOS semiconductor device and a method of making the device. A polysilicon gate post rises normal to a surface of a substrate. An annular transistor encircles the gate post. The transistor consists of a channel layer sandwiched between a pair of source/drain layers. Each layer lies directly above the layer beneath, with the gate post projecting up through the layers. One or more additional transistors of the same or differing polarities may be stacked above the first transistor, the various transistors being suitably spaced apart from each other. Electrical connections with the gate post and the various source/drain layers may be configured to provide a complementary inverter or some other circuit as desired.

REFERENCES:
patent: 4622569 (1986-11-01), Lade et al.
patent: 4951102 (1990-08-01), Beitman et al.

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