Parallel/serial conversion circuit, serial/parallel conversion c

Details Parallel/serial conversion circuit, serial/parallel conversion c Parallel/serial conversion circuit, serial/parallel conversion c

1992-12-14

1994-06-14

Williams, Howard L.

Coded data generation or conversion

Digital code to digital code converters

Serial to parallel

341101, 3072722, 307452, 377 81, H03M 900

Patent

active

053213998

ABSTRACT:
A ratio latch included in each slave latch is formed of a tri-state inverter and a weak inverter. During a period when a parallel input signal is supplied to the ratio latch in each master latch in response to a trigger clock signal, the tri-state inverter attains a high impedance state in response to an inverted trigger clock signal.

REFERENCES:
patent: 4418418 (1983-11-01), Aoki
patent: 4775990 (1988-10-01), Kamuro et al.
patent: 4799040 (1989-01-01), Yanagi
patent: 5132993 (1992-07-01), Nishiura et al.
patent: 5264738 (1993-11-01), Veendrick et al.
"Introduction to nMOS and CMOS VLSI Systems Design", by Amar Mukherjee, pp. 213-217.
Suzuki et al.; Clocked CMOS Calculator Circuitry; IEEE Journal of Solid State Circuits, vol. SC-8, No. 6; Dec. 1973, pp. 462-469.

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