Method for reducing the spacing between the horizontally-adjacen

Details Method for reducing the spacing between the horizontally-adjacen Method for reducing the spacing between the horizontally-adjacen

1995-04-28

1996-10-15

Nguyen, Viet Q.

Static information storage and retrieval

Floating gate

Particular biasing

36518501, 365182, 3651851, 257315, 257316, 257319, H01L 27115, H01L 2182, H01L 2122

Patent

active

055661068

ABSTRACT:
The spacing between the horizontally-adjacent floating gates of a "T-shaped" flash electrically programmable read-only-memory (EPROM) array is reduced beyond that which can be photolithographically obtained with a given process by covering the layer of polysilicon that forms the floating gates with two sacrificial layers, exposing strips of the polysilicon layer with a standard photolithographic process, forming spacers that protect a portion of the exposed polysilicon layer, and then etching the layer of polysilicon that remains exposed.

REFERENCES:
patent: 4851365 (1989-07-01), Jeuch
patent: 4868619 (1989-09-01), Mukherjee et al.
patent: 5011787 (1991-04-01), Jeuch
patent: 5120670 (1992-06-01), Bergemont
patent: 5212541 (1993-05-01), Bergemont
patent: 5284784 (1994-02-01), Manley

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