Semiconductor device

Details Semiconductor device Semiconductor device

1987-06-08

1991-07-02

Hille, Rolf

357 67, H01L 2354

Patent

active

050289829

ABSTRACT:
To cover the interconnection (2) on a semiconductor device (1) at high speed with an insulating film (3) having good step coverage, a dummy pattern (8) is provided around the interconnection (2) and the dummy pattern (8) and the interconnection (2) are covered with the insulating film (3) using the bias sputtering method.

REFERENCES:
patent: 3868723 (1975-02-01), Lechaton et al.
patent: 4524508 (1985-06-01), Sato
Patent Abstracts of Japan, vol. 9, No. 61, Mar. 19, 1985, "Manufacture of Wiring Structure", Tooru Mogami.
"Study of Planarized Sputter-Deposited SiO.sub.2 ", by C. Y. Ting et al., Journal of Vacuum Science and Techology, vol. 15, No. 3, May/Jun., 1978, pp. 1105-1112.
"SiO.sub.2 Planarization by RF Bias Sputtering", by T. Mogami et al., 25th Symposium on Semiconductor Integrated Circuits Technique, Dec. 26, 1983.

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