Low di/dt BiCMOS output buffer with improved speed

Details Low di/dt BiCMOS output buffer with improved speed Low di/dt BiCMOS output buffer with improved speed

1990-11-05

1992-08-18

Westin, Edward P.

Electrical transmission or interconnection systems

Nonlinear reactor systems

Parametrons

307443, 3072968, 307270, H03K 19092, H03K 1716

Patent

active

051401916

ABSTRACT:
An output buffer for a device such as a memory comprises a voltage regulator, a current source portion, a switching portion, and an output portion. The voltage regulator provides a constant voltage independent of fluctuations between first and second power supply voltages. The current source portion provides first and second currents to first and second nodes to limit the rate at which transistors in the output portion become conductive. The switching portion provides voltage signals on the first and second nodes respectively in response to positive and negative voltage differences between first and second input voltages. The output portion provides an output signal at either a logic high or a logic low voltage respectively in resonse to the voltage signals at the first and second nodes. The current source portion allows the use of faster bipolar transistors to improve the speed of the output buffer while maintaining accepable di/dt.

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Tran et al., "An 8ns BicMOS 1Mb ECL SRAM with a Configurable Memory Array Size", 1989, IEEE Solid State Circuits Conf., pp. 36-37.
Kertis et al., "A 12ns 256K BiCMOS SRAM", 1989 IEEE Solid State Circuits Conference, pp. 186-218.
Burnett and Hu, "Hot-Carrier Degradation in Bipolar Transistors at 300 and 110K-Effect on BiCMOS Inverter Performance", IEEE Transactions on Electron Devices, vol. 37, #4, Apr. 1990, pp. 1171-1173.
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"A 25ns Full-CMOS 1Mb SRAM", IEEE International Solid State Circuits Conference, Feb. 1988, pp. 178-179, List et al.

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