Process for fabricating polysilicon resistors and interconnects

Details Process for fabricating polysilicon resistors and interconnects Process for fabricating polysilicon resistors and interconnects

1991-01-28

1992-04-28

Quach, T. N.

Fishing, trapping, and vermin destroying

437 41, 437 59, 437193, 437918, 148DIG136, H01L 21335, H01L 21283

Patent

active

051089459

ABSTRACT:
A process for faricating polysilicon resistors and polysilicon interconnects coupled to MOS field-effect devices in a silicon substrate includes the steps of depositing and etching a first polysilicon layer to form the gates of the MOS devices; then depositing a second layer of polysilicon between the gates. The second polysilicon layer is then etched so that its upper surface is substantially coplanar with the gates. Contact openings are then defined to the source, drain and gate members of the devices through an insulative layer formed over the first and second polysilicon layers. Next, a metal layer is deposited to fill the openings and is patterned to define electrical contacts to the devices. The patterning step also defines the interconnect lines in the metal layer. A third polysilicon layer is then deposited and patterned to define the polysilicon resistors and interconnects.

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Ku, S. M., "Ohmic Contacts . . . ", IBM Technical Disclosure Bulletin, vol. 22, No. 4, Sep. 1979, pp. 1487-1488.
Ghandhi, S. K., VLSI Fabrication Principles, John Wiley & Sons, 1983, pp. 420-437.

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