Master slice integrated circuit having a memory region

Details Master slice integrated circuit having a memory region Master slice integrated circuit having a memory region

1989-05-03

1992-04-28

Chaudhuri, Olik

Fishing, trapping, and vermin destroying

437 52, H01L 2170

Patent

active

051089424

ABSTRACT:
A gate array chip (33) has an array (41) of strip-shaped active areas (18) formed on a semiconductor substrate (40). Wiring-dedicated areas (34), each having capacity for two to four wires, are provided between respective adjacent pairs of the active areas (18). In a logic circuit region, one or more active areas (18) are employed as wiring areas. In memory blocks, wiring is performed by employing only the wiring-dedicated areas (34). A master slice integrated circuit manufactured from the gate array chip (33) has a high degree of integration and high operating speed.

REFERENCES:
patent: 4623911 (1986-11-01), Pryor
patent: 4783692 (1988-11-01), Uratani
IEEE Journal of Solid State Circuits, vol. SC-20, No. 5 Oct. 1985, A 240K Transistor CMOS Array with Flexible Allocation of Memory and Channels, Horomasa Takahashi et al.

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