Self-aligned JFET

Details Self-aligned JFET Self-aligned JFET

1997-09-19

1999-01-19

Prenty, Mark V.

Active solid-state devices (e.g., transistors, solid-state diode

Field effect device

Junction field effect transistor

257263, H01L 2980

Patent

active

058616438

ABSTRACT:
A JFET device is formed on a semiconductor body comprising an active region for the junction field effect device. A drain region layer is formed below the lower portion of the active region. The top surface of the body is doped to provide a source region layer on the device. Gate trenches extend through the source region layer forming source regions therein. The gate trenches also extend partially through the epitaxial layer. The gate trenches have sidewalls and bottoms. Dielectric spacer layers cover the sidewalls of the gate trenches upon surfaces of the source layer and the epitaxial layer in the gate trenches. Self-aligned gate regions are formed at the bottoms of the gate trenches in doped portions of the active region.

REFERENCES:
patent: 5243209 (1993-09-01), Ishii
patent: 5294814 (1994-03-01), Das

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