Low resistance backside preparation for semiconductor integrated

Details Low resistance backside preparation for semiconductor integrated Low resistance backside preparation for semiconductor integrated

1983-01-24

1984-06-12

Smith, John D.

357 67, 357 71, H01L 21285

Patent

active

044545282

ABSTRACT:
To provide an electrically conductive p-type wafer backside for semiconductor integrated circuit chips (die), a process is provided consisting of applying a thin layer of aluminum on a silicon dioxide free surface of the chip, followed by a layer of gold, then alloying the metals to diffuse the gold and traces of aluminum into the chip surface. The surface thus prepared can then be advantageously die attachable to a receiving surface by either eutectic alloy or conductive polymer techniques.

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