Process for manufacturing an interconnection substrate to connec

Details Process for manufacturing an interconnection substrate to connec Process for manufacturing an interconnection substrate to connec

1996-06-05

1999-01-19

Quach, T. N.

Semiconductor device manufacturing: process

Packaging or treatment of packaged semiconductor

Assembly of plural semiconductive substrates each possessing...

438119, 438617, H01L 2160

Patent

active

058613226

ABSTRACT:
The process includes the following steps: forming a layer of meltable material (102) on an initial substrate (100); forming a first layer of dielectric material (104) and engraving this layer (104) to form openings (106) therein; forming metal blocks (108) in the openings (106); depositing a metal layer (110) covering the blocks; engraving the metal layer (110) to form conducting tracks (112); forming a layer of dielectric material (114) covering the conducting tracks and engraving this layer (114) to form openings therein; forming metal blocks (118) in these openings; separating the interconnection substrate from the initial substrate by heating the meltable material to a temperature equal to or exceeding its melting temperature.

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patent: 5635427 (1997-06-01), Takahashi
"Ball Grid Array", TechSearch International, Inc., 1994, Month Not Known, 7 pages.
"Thin Film Transfer Process for Low Cost MCM-D Fabrication", IEEE Transactions on Components..., Part B, vol. 18, No. 1, Feb. 1995, pp. 42-46.
"Planarized Testing Pads for Thin Films in Serial Parallel process" IBM Technical Disclosure Bulletin, vol. 36, No. 6B, Jun. 1993, pp. 173-174.

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