Partial response, quadrature amplitude modulation system

Telegraphy – Systems – Chemical

Patent

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Other Related Categories

178 67, 325 38A, H04L 1500

Type

Patent

Status

active

Patent number

040557278

Description

ABSTRACT:
A communication system combines partial response and quadrature amplitude modulation systems. Two parallel input signals supplied for transmission are processed by a differential logic circuit which produces two parallel output signals, in turn supplied to respective pre-coding circuits and subsequently to corresponding partial response converter circuits. Corresponding modulators receive the thus processed two parallel signals for amplitude modulation of respective quadrature-related carrier signals and for combining same for QAM transmission. The differential logic circuit examines the parallel input signals and, for a code combination thereof wherein the code combination would not be influenced by the 90.degree. phase ambiguity of the regenerated carrier during demodulation in the receiver, the parallel input signals received thereby are applied directly to the pre-coding circuits; conversely, where the code combination of the parallel input signal code combination would be influenced by the 90.degree. phase ambiguity of the regenerated carrier during the aforesaid demodulation, the two parallel input signals are processed in accordance with the differential logic processing prior to supply to the pre-coding circuit. Particularly, when the input signals P.sub.n, Q.sub.n are (1,1) or (0,0), they are applied directly to the pre-coding circuit; when (0,1) the preceding transmitting vector position is maintained, and when (1,0), the differential logic changes the phase thereof by .+-.90.degree. from the preceding transmitting vector position. The preceding transmitting vector is defined as that vector corresponding to the next preceding signal code combination (1,0) or (0,1), skipping any vector corresponding to a code combination (0,0) or (1,1) which may intervene. In the receiver, a corresponding differential logic circuit is provided, whereby the output data in the receiver is accurately reproduced in accordance with the originally transmitted data, independently of the phase ambiguity of the phase of the regenerated carrier in the receiver.

REFERENCES:
patent: 3679977 (1972-07-01), Howson
patent: 3806807 (1974-04-01), Nakamura
patent: 3829779 (1974-08-01), Fujimoto
patent: 3845412 (1974-10-01), Rearwin
patent: 3849595 (1974-11-01), Ishiguro
patent: 3947767 (1976-03-01), Koike

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