Computer graphics processing and selective visual display system – Display driving control circuitry – Controlling the condition of display elements
Patent
1991-09-18
1997-11-11
Lane, Jack A.
Computer graphics processing and selective visual display system
Display driving control circuitry
Controlling the condition of display elements
345412, G06F 1202
Patent
active
056873425
ABSTRACT:
A split-range address detector and translator for interfacing a system processor with a memory array. The split-range detector generates a select signal for the memory array whenever an input address received from the system processor resides in either of two, non-contiguous, address ranges. The split-range detector includes a first range detector which generates a first range detection signal when the address received from the system processor is within a first, lower, range of addresses, and a second range detector which generates a second range detection signal when the input address is within a second, upper, range of addresses. The output signals are combined together to produce the select signal for the memory array. The address ranges are defined by upper and lower address limits stored within programmable registers. The address translator includes subtraction logic which determines the size of the address gap between the two address ranges from the stored address limits and generates a translated address by subtracting the size of the address gap from the input address. A bus multiplexer responsive to the second range detection signal provides the input address information to the memory array when the input address is within the lower address range and provides the translated address to the memory array when the input address is within the upper range of addresses. Thus, addresses received from the system processor are mapped into a single contiguous address space within the memory array.
REFERENCES:
patent: 3813652 (1974-05-01), Elmer et al.
patent: 4025903 (1977-05-01), Kaufman et al.
patent: 4400794 (1983-08-01), Koos
patent: 4414627 (1983-11-01), Nakamura
patent: 4571676 (1986-02-01), Mantellina et al.
patent: 4727475 (1988-02-01), Kiremidjian
patent: 4860252 (1989-08-01), Sukara
patent: 4922451 (1990-05-01), Lo et al.
patent: 4980850 (1990-12-01), Morgan
patent: 5119486 (1992-06-01), Albonesi
Lane Jack A.
NCR Corporation
Stover James M.
LandOfFree
Memory range detector and translator does not yet have a rating. At this time, there are no reviews or comments for this patent.
If you have personal experience with Memory range detector and translator, we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Memory range detector and translator will most certainly appreciate the feedback.
Profile ID: LFUS-PAI-O-1236559