Patent
1996-03-15
1997-11-11
Meky, Moustafa M.
G06F 1100
Patent
active
056873107
ABSTRACT:
An apparatus which provides a means of ensuring command synchronization for computer systems employing sliced gate array processors includes a computer bus, a plurality of central processing units and a plurality of input/output processors coupled to the computer bus. Each input/output processor includes means to receive commands from said central processing units. The apparatus further includes means within each of the input/output processors for generating a signal indicating the type of command received from the central processing units and means for receiving from every other input/output processor the command type signal generated by every other input/output processor. In addition, the apparatus further includes means for comparing said command type signals and generating an error signal when the comparison indicates that all of the input/output processors have not received the same command.
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Hinrichs Randall Dean
Rotker Paul Stuart
Digital Equipment Corporation
Drozenski Diane C.
Fisher Arthur W.
Hudgens Ronald C.
Meky Moustafa M.
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