Multi-mode cache structure

Details Multi-mode cache structure Multi-mode cache structure

1996-03-22

1997-11-11

Fears, Terrell W.

Static information storage and retrieval

Addressing

36518907, 36523008, G11C 1300

Patent

active

056871317

ABSTRACT:
A multimode cache structure includes a predefined block of memory and controls for that block of memory which allow the memory block to perform multiple functions. The selectable, multiple functions include a cache mode, a SRAM mode, a flush mode and an invalidate mode. A control register is defined and is associated with the predefined memory block, which control register includes multiple status bits therein. Each of the status bits corresponds to one of the multiple functions and, when a particular status bit is set, the predefined block of memory performs a function corresponding to the status bit that is set.

REFERENCES:
patent: 5363330 (1994-11-01), Kobayashi et al.
"The ARM RISC Chip, A Programmer's Guide" Alex van Someren & Carol Atack, 1993, pp. 21-35, Addison-Wesley Publishing Company.
"ARM7DI Data Sheet" Advanced RISC Machines Ltd. (ARM), Dec., 1994, pp. ii, 15-18, 81-90, 119-129.
"ARM Software Development Toolkit 2.0" Advanced RISC Machines Ltd. (ARM), prior to Jan. 1, 1996, 3 pages.
"An Introduction to Thumb" Advanced RISC Machines Ltd. (ARM), Mar. 1995, pp. 9-14.

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