Net list for use in logic simulation and back annotation method

Details Net list for use in logic simulation and back annotation method Net list for use in logic simulation and back annotation method

1994-05-13

1997-11-11

Teska, Kevin J.

Boots, shoes, and leggings

364489, 364578, 395500, G06F 1560

Patent

active

056870884

ABSTRACT:
In a net list for use in logic simulation, a specific node connection having a coupled capacitance with a different node connection is provided with a delay adding means. The delay adding means has a table consisting of correction values for correcting a delay which correspond to delay variations caused by the coupled capacitance. To the delay adding means is transmitted the initial state, transition direction, and transition time of the logic output of a first logic cell for driving the above specific node connection. To the delay adding means is also transmitted, by means of a virtual connection for capacitive coupling, the initial state, transition direction, and transition time of the logic output of a second logic cell for driving the above different node connection. In this manner, the delay adding means selects a correction value from the above table and add the delay, in which the influence of the capacitive coupling is taken into account, to the logic output of the above first logic cell.

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