Built-in self-test system and method for self test of an integra

Details Built-in self-test system and method for self test of an integra Built-in self-test system and method for self test of an integra

1991-05-28

1996-05-07

Beausoliel, Jr., Robert W.

Excavating

G01R 3128

Patent

active

055153836

ABSTRACT:
A built-in self-test system and method for use in testing an integrated circuit. An integrated circuit (200) includes a self-test generator (210) that produces pseudo-random test vectors, each having fewer bits than a normal input signal applied to the integrated circuit. The normal signal comprises data and parity bits that are applied to a plurality of error detection and correction (EDAC) circuits (50) on the integrated circuit. Selected bits of the pseudo-random test vectors generated by the self-test generator are fanned out to provide the total number of bits of the data and parity signals, and a test signature is produced after a full set of test vectors have been processed by the EDAC. A signature analyzer (222) compares the test signature with a predetermined expected signature to determine if a fault has occurred in one of the EDACs in the integrated circuit. The self test can be made upon demand, or alternatively, can be run pseudo-concurrently with the normal mode, using cycle stealing.

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