Patent
1975-08-19
1977-08-09
Wojciechowicz, Edward J.
357 23, 357 41, 357 51, 357 59, H01L 2702, H01L 2978, H01L 2904
Patent
active
040415228
ABSTRACT:
An integrated circuit comprises complementary FET having channels extending on the surface of a substrate and on the surface of a well in the substrate and gates formed in a layer of polycrystalline silicon insulated from the substrate and from each said well. A floating diode, i.e. connected neither to the substrate, nor to a well, is formed simultaneously with the FET by depositing and selectively etching a first doped oxide to cover a first region of the polycrystalline silicon, depositing an oppositely doped oxide over the remainder using the first oxide as mask, and oppositely doping the two regions of polycrystalline silicon by heat treatment. Alternatively, the second region can be doped by treatment in a gaseous phase or by ionic implantation, in either case using the first oxide as mask. Said regions are contiguous under the edge of the first doped oxide to form an autoaligned junction forming said floating diode which has a reverse conductivity notably greater than that of a junction in monocrystalline silicon, and easily reproduceable characteristics.
REFERENCES:
IBM Tech. Bul., vol. 14, No. 11, Apr. 1972, p. 3255, Doo et al., "Dynamic SCR Memory with Poly-Si-Diode".
Electronics, Aug. 30, 1971, pp. 38-43, Burgess et al., "C/MOS Unites with Silicon Gate...".
Gerber Bernard
Oguey Henri J.
Centre Electronique Horloger S.A.
Wojciechowicz Edward J.
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