Process for fabricating flash memory devices

Details Process for fabricating flash memory devices Process for fabricating flash memory devices

1995-11-13

1997-11-11

Nguyen, Viet Q.

Fishing, trapping, and vermin destroying

437 48, 437 52, 437 49, 437228, 437225, H01L 218247

Patent

active

056863322

ABSTRACT:
A process for fabricating on a semiconductor substrate flash memory devices capable of sustaining a high-efficiency memory erasure operation. A number of field oxide layers and gate oxide layers are first formed over the substrate. A number of first conducting layers are then formed over the field oxide layers and gate oxide layers in a first direction. Ions are implanted into the substrate to form bit lines. Gate dielectric layers are then formed over the first conducting layers. A number of second conducting layers are then formed with two sidewalls to constitute word lines. First spacers are then formed over the sidewalls of the second conducting layers. The gate dielectric layer and first conducting layer are etched into floating gates. The first spacers are then removed. Second and third spacers are then formed for the second conducting layers and the floating gates to reveal a portion of the gate dielectric layer at the edges of the floating gates. The revealed portion of the gate dielectric layer is then removed to form open windows for tunnel oxide layers. A number of third conducting layers are then formed over the tunnel oxide layers as erase gates for the flash memory device.

REFERENCES:
patent: 5198380 (1993-03-01), Harari
patent: 5268319 (1993-12-01), Harari
patent: 5534456 (1996-07-01), Juan et al.
patent: 5541130 (1996-07-01), Ogura et al.
patent: 5554553 (1996-09-01), Harari
patent: 5595924 (1997-01-01), Juan et al.

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