Semiconductor memory device containing a cache and an operation

Details Semiconductor memory device containing a cache and an operation Semiconductor memory device containing a cache and an operation

1990-06-25

1993-01-12

Bowler, Alyssa H.

Boots, shoes, and leggings

364DIG1, 36424341, 365 49, 365193, G06F 1208, G06F 1300, G11C 700

Patent

active

051796872

ABSTRACT:
A DRAM for use in a simple cache memory system comprises a memory cell array divided into a plurality of blocks, a plurality of data registers provided corresponding to the respective blocks of the array for latching memory cell data of the corresponding blocks, and a selector responsive to a row address strobe signal for selecting access to either the data registers or the memory cell array. Upon cache hit, the row address strobe signal is inactivated to cause the selector to select the access to the data registers. Upon cache miss, the row address strobe signal is activated to cause the selector to select the access to the memory cell array.

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