Cross-point eeprom memory array

Static information storage and retrieval – Floating gate

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365 63, 365218, 257314, 257316, G11C 1140

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active

054673089

ABSTRACT:
A cross-point EEPROM memory array includes a semiconductor substrate (10) having first and second bit-lines (32, 34) spaced apart by a channel region (36). A control gate electrode (24) is formed by a portion of a control gate line, which overlies a first portion of the channel region (36) and is separated therefrom by an ONO layer (17). A select gate electrode (40) is formed by a portion of a select gate line disposed on the substrate (10) perpendicular to the control gate line. Individual cells in the array are programmed by injecting electrons using source-side injection into trapping sites (19) in the silicon nitride layer (14) of the ONO layer (17). The cells in the array are erased by electron tunneling through the top silicon dioxide layer (16) of the ONO layer (17), and are dissipated in the control gate electrode (24). Improved operating performance is obtained, in part, by fabricating the first silicon dioxide layer (12) of the ONO layer (17) to a greater thickness than the top silicon dioxide layer (16) of the ONO layer (17).

REFERENCES:
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patent: 5051793 (1991-09-01), Wang
patent: 5063172 (1991-11-01), Manley
patent: 5231299 (1993-07-01), Ning et al.
patent: 5241193 (1993-08-01), Pfiester et al.
patent: 5280446 (1994-01-01), Ma et al.
T. Y. Chan et al., "A True Single-Transistor Oxide-Nitride-Oxide EEProm Device", IEEE EDL-8, No. 3, Mar. 1987, pp. 93-95.
Yoshimitau Yamauchi, et al., "A 5V-only Virtual Ground Flash Cell with an Auxiliary Gate for High Density and High Speed Application", IEDM 1991, pp. 319-322.
K. Naruke, et al., "A New Flash-Erase EEPROM Cell with a Sidewall Select-Gate on its Source Side", IEDM 1989, pp. 603-606.
A. T. Wu, "A Novel High-Speed, 5-Volt Programming Eprom Structure", 1986 IEEE, pp. 584-587.

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