High-speed small digital multiplier

Details High-speed small digital multiplier High-speed small digital multiplier

1994-05-31

1995-11-14

Envall, Jr., Roy N.

Boots, shoes, and leggings

364737, 364745, G06F 752, G06F 738, G06F 1100

Patent

active

054672961

ABSTRACT:
A digital multiplier absolutizes a multiplicand and a multiplier for decreasing component bits thereof, and multiplies the absolutized multiplicand by the absolutized multiplier for producing a product without a sign bit; the sign bits are produced from the multiplicand and the multiplier independent from the multiplication, and the sign bits are added to the data code indicative of the product; the component circuits for producing partial products are decreased, and the multiplication is speed-up.

REFERENCES:
patent: 4649508 (1987-03-01), Kanuma
patent: 4722066 (1988-01-01), Armer et al.
patent: 4945507 (1990-07-01), Ishida et al.
patent: 5038313 (1991-08-01), Kojima
patent: 5262973 (1993-11-01), Richardson
"Observation of Architecture for Multiplier in Parallel Processing Along LSI Technologies"; Nikkei Electronics, 1978; pp. 77-89.

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