Method and system for dynamically translating bus addresses with

Details Method and system for dynamically translating bus addresses with Method and system for dynamically translating bus addresses with

1997-01-27

1999-03-30

Sheikh, Ayaz R.

395836, 395308, 395306, 395828, 395830, G06F 1300

Patent

active

058900110

ABSTRACT:
A method for dynamically translating bus address within a computer system is disclosed. In accordance with the method and system of the present invention, a computer system has a multiple of buses connected in a hierarchial manner. Information concerning a bus and a device attached to a bus are stored in a Hardware Namespace. In response to a request for an access to a device attached to one of the buses for the first time, a determination is made from the Hardware Namespace as to whether or not there is resource available for the device in a parent bus of the device. If there is resource available in the parent bus for the device, another determination is made from the Hardware Namespace as to whether or not the resource is exclusively allocated in the parent bus for the device. If the resource is exclusively allocated in the parent bus for the device, the device is configured according to the available resource. If the resource is not exclusively allocated in the parent bus for the device, the process resolves through each level of buses in the hierarchy until a bus having a resource that can be allocated for the device is found such that the device can be added to any one of the buses within the computer system independent of bus technology.

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IBM Technical Disclosure Bulletin, vol. 38, No. 01, Jan. 1995, "Exporting a Subset of Virtual Address Bits for L2 Support".

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