Fishing – trapping – and vermin destroying
Patent
1994-02-15
1995-11-14
Thomas, Tom
Fishing, trapping, and vermin destroying
437 43, 437 48, 437904, H01L 218247
Patent
active
054666228
ABSTRACT:
A process for simultaneously fabricating memory cells, transistors, and diodes for protecting the tunnel oxide layer of the cells, using the DPCC process wherein the first polysilicon layer is not removed from the transistor area, and the gate regions of the transistors are formed by shorted first and second polysilicon layers. To form the diodes, the polyl layer is removed from the active areas in which the diodes are to be formed, using the same mask employed for shaping polyi; the interpoly dielectric layer and the gate oxide layer are removed from the active areas of the diodes, using the same mask employed for removing the dielectric layer from the transistor area; a second polysilicon layer is deposited directly on to the active areas of the diodes; and the poly2 doping ions penetrate the active areas to form N+ regions which, together with the substrate, constitute the protection diodes. The diodes are thus formed prior to shaping poly2, and are connected to the control gates of the cells by the second polycrystalline silicon layer strips forming the word lines.
REFERENCES:
patent: 4635347 (1987-01-01), Liem et al.
patent: 4775642 (1988-10-01), Chang et al.
patent: 5036018 (1991-07-01), Mazzali
patent: 5183773 (1993-02-01), Miyata
SGS-Thomson Microelectronics S.R.L.
Thomas Tom
LandOfFree
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