Miscellaneous active electrical nonlinear devices – circuits – and – Signal converting – shaping – or generating – Clock or pulse waveform generating
Patent
1997-02-03
1999-03-30
Wells, Kenneth B.
Miscellaneous active electrical nonlinear devices, circuits, and
Signal converting, shaping, or generating
Clock or pulse waveform generating
327 99, 327147, 327161, 327292, 375376, H03K 300
Patent
active
058894233
DESCRIPTION:
BRIEF SUMMARY
BACKGROUND OF THE INVENTION
The invention relates to a method and a circuit arrangement for obtaining a timing signal.
In digital data transmission systems, the bit timing at the receiving end can be obtained from the received digital data signal by means of clock recovery circuits. When phase locked loops are used for clock recovery from a digital data stream, only pure phase comparators (phase-sensitive phase detectors) may be used since no phase correction flank is available with every bit clock pulse but, depending on the envisaged coding, for example on average only every three bit clock pulses. As is known, these pure phase comparators have the disadvantage that circuits constructed in this way also lock onto harmonic frequencies and even attempt to do this (unsuccessfully) at other frequencies. In order to avoid these disadvantages, voltage-controlled oscillators have been used until now having a mid-frequency which is in each case defined accurately and corresponds to the nominal value of the bit clock rate, as well as a very small frequency shift, precise frequency-determining elements being required to implement such voltage-controlled oscillators (cf. Deutsche Bundespost Information Leaflets, Year 34/1981, No. 2, page 81).
PLL (Phase Locked Loop) circuits are used in digital data transmission networks, for example in SDH (Synchronous Digital Hierarchy) transmission systems, to produce the transmission clock. The phase locked loop compares the filling level of a buffer store with its nominal value, and corrects the transmission frequency accordingly. The nominal transmission frequency is defined by the mid-frequency of the phase locked loop. The actual transmission frequency is determined by pulling the phase locked loop via its control voltage on the basis on the quantity of data which occurs. The signal which indicates the discrepancy between the filling level of the buffer store and the nominal value is provided by a discrete signal having a low rate of state changes in comparison with the transmission frequency. Integrated voltage-controlled oscillators VCOs which are known per se cannot be used for this application because of the occasional correction, since their short-term stability is insufficient by a wide margin in terms of the accuracy requirements for synchronous data networks.
In this application as well, circuits are normally used in which a phase locked loop controls a voltage-controlled, crystal-stabilized oscillator VCXO (Voltage-Controlled Xtal (=crystal) Oscillator). These voltage-controlled, crystal-stabilized oscillators require accurate frequency-determining elements for stabilization.
The frequency-determining elements, which can be provided by narrowband filters or tuned circuits and which can be implemented, for example, using surface acoustic wave, crystal or ceramic filters cannot directly be integrated together with the rest of the circuit in a chip, so that the frequency-determining elements must be arranged outside the chip, for which purpose additional connections to the chip must be provided, additional space is required on the assembly, and additional outlay is required for fitting the assembly with components.
SUMMARY OF THE INVENTION
In digital transmission systems in which a plurality of data signals which are not locked in phase to one another are intended to be received or transmitted simultaneously, the complexity is evident in a particularly disturbing manner since a separate phase locked loop must be provided for each data signal, each phase locked loop having accurate frequency-determining elements. The invention is based on the problem of specifying a method and a circuit arrangement for obtaining a timing signal, in the case of which method and circuit arrangement precise external or trimming frequency-determining elements are avoided.
The essential features for solving the problem are provided in that controlled delay line (VCD0, VCD1), a phase comparator (PV0, PV1) and a loop filter (LF0, LF1) and whose control voltages can be driven in a control
REFERENCES:
patent: 5150068 (1992-09-01), Kawashima et al.
Patent Abstracts of Japan, vol. 8, No. 149, (E-255), 12 Jul. 1984 and JP59-054344 dated 29 Mar. 1984.
Siemens Aktiengesellschaft
Wells Kenneth B.
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