Emulating a delayed exception on a digital computer having a cor

Details Emulating a delayed exception on a digital computer having a cor Emulating a delayed exception on a digital computer having a cor

1996-02-15

1998-07-07

Voeltz, Emanuel Todd

395527, 395595, G06F 900, G06F 946

Patent

active

057782113

ABSTRACT:
A digital computer system comprises a precise exception handling processor and a control subsystem. The precise exception handling processor performs processing operations under control of instructions. The precise exception handling processor is constructed in accordance with a precise exception handling model, in which, if an exception condition is detected in connection with an instruction, the exception condition is processed in connection with the instruction. The precise exception handling processor further includes a pending exception indicator having a pending exception indication state and a no pending exception indication state. The control subsystem provides a series of instructions to the precise exception handling processor to facilitate emulation of at least one emulated program instruction. The emulated program instruction is constructed to be processed by a delayed exception handling processor which is constructed in accordance with a delayed exception handling model, in which if an exception is detected during processing of an instruction, the exception condition is processed in connection with a subsequent instruction. The series of instructions provided by the control subsystem in emulation of the emulated program instruction controls the precise exception handling processor to

REFERENCES:
patent: 5113521 (1992-05-01), McKeen et al.
patent: 5197138 (1993-03-01), Hobbs et al.
patent: 5237700 (1993-08-01), Johnson et al.
patent: 5406644 (1995-04-01), MacGregor

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