Technique for passivating semiconductor devices

Details Technique for passivating semiconductor devices Technique for passivating semiconductor devices

1975-04-21

1977-02-08

Lynch, Michael J.

357 38, 357 64, 357 73, H01L 2934

Patent

active

040074765

ABSTRACT:
The specification discloses a technique for passivating a semiconductor device which includes exposing a P-N junction in a multilayered semiconductor body. A mixture of glass and gold is prepared and applied to the exposed P-N junction. A mixture is fired to fuse the glass and gold on the semiconductor body. The carrier lifetime degrading characteristics of the gold reduces the current leakage at the exposed P-N junction. The technique substantially improves the voltage capacity and stability of semiconductor switching devices.

REFERENCES:
patent: 3376172 (1968-04-01), Byczkowski
patent: 3493405 (1970-02-01), Thomas
patent: 3632434 (1972-01-01), Hutson
patent: 3637425 (1972-01-01), McMillan et al.

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