System having control registers coupled to a bus whereby address

Details System having control registers coupled to a bus whereby address System having control registers coupled to a bus whereby address

1991-09-27

1994-02-15

Lee, Thomas C.

Boots, shoes, and leggings

3642292, 364247, 364DIG1, G06F 1200

Patent

active

052875032

ABSTRACT:
A computer storage register architecture permitting secure atomic access to set or clear one or more particular bits wherein a multiple bit register is disclosed. In the preferred embodiment, a multiplicity of unique addresses is assigned to a multiple bit register. One address constitutes a read address, one address constitutes a clear address, and a third address constitutes a set address. An address decoder decodes the addresses assigned to the register so that only that register is accessed for the associated read, clear, and set operations, respectively. Data having a register position equivalent binary pattern of logical zeros and ones corresponding to particular bit locations of the register to be set or cleared are associated with the set and clear addresses. If the position equivalent binary value of the data associated with the address decoded is a logical one, then the corresponding bit in the register will be set or cleared. Otherwise, the bit remains unchanged.

REFERENCES:
patent: 4085106 (1989-02-01), Pfeifer
patent: 4086658 (1978-04-01), Finlay
patent: 4149264 (1979-04-01), Hamada et al.
patent: 4194241 (1980-03-01), Mager
patent: 4520439 (1985-05-01), Liepa
patent: 4663728 (1987-05-01), Weatherford et al.
patent: 4862155 (1989-08-01), Dalrymple et al.
patent: 5201039 (1993-04-01), Sakamura

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