Vector translator

Details Vector translator Vector translator

1997-02-03

1998-07-07

Beausoliel, Jr., Robert W.

Excavating

371 271, G01R 3128

Patent

active

057780048

ABSTRACT:
A technique for accepting test vectors in one format, generally proven to operate correctly, from an IC tester such as the Logic Master XL2 ("off-bench tester") and processing/converting them into another format for use in a stimulus generator such as the HFS 9009 for bench top testing. The process, which in the exemplary embodiment is implemented in software, accepts various parameters as inputs (e.g., channel name(s) for stimulus generator, range of vectors, etc.) for purposes of extraction and translation. The process provides an Interface and Initialization Unit (IIU) and a Translator Unit (TU). The IIU provides a user interface necessary for a user to select the various options available. In addition, the IIU coordinates the use of memory, file I/O and communication with the active files on the off-bench tester. The IIU verifies user selections and does error checking. Once complete, the TU translates the selected signals for the vector range entered by the user. Data is temporarily stored in memory and then written to a VCA format output file in records. Additionally, the TU automatically expands all encountered pattern instructions (e.g., REPEAT, LOOP, etc.) into equivalent vectors before writing to memory. The TU also does verification and error checking. Once the TU 112 generates a completed VCA file, the vectors are ready to be downloaded to the stimulus generator.

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