Solid state imager having high frequency transfer mode

Television – Camera – system and detail – Solid-state image sensor

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Details

348303, 358483, H04N 314, H04N 5335

Patent

active

057776717

ABSTRACT:
A control circuit generates a control signal which is of a low level during a certain period of time after the power supply of a solid state imager has been turned on or a power save mode thereof has been canceled, and of a high level after elapse of the period of time. Based on the control signal, a timing generator generates transfer clock signals having a high frequency than when the solid state imager is in a normal transfer mode, and applies the transfer clock signals to a CCD shift register to remove or transfer excessive invalid charges at a high rate therefrom. After the power supply has been turned on or the power save mode has been canceled, therefore, the time required to bring the solid state imager into a condition capable of imaging a subject is shortened.

REFERENCES:
patent: 3800169 (1974-03-01), Diaz
patent: 4686571 (1987-08-01), Suzuki
patent: 4862273 (1989-08-01), Ishida et al.
patent: 4958183 (1990-09-01), Akada et al.
patent: 5057926 (1991-10-01), Watanabe
patent: 5083207 (1992-01-01), Ishida et al.
patent: 5097339 (1992-03-01), Ishida et al.

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