V-MOS Device with self-aligned multiple electrodes

Details V-MOS Device with self-aligned multiple electrodes V-MOS Device with self-aligned multiple electrodes

1980-06-12

1982-12-14

Edlow, Martin H.

357 41, 357 55, H01L 2978

Patent

active

043640745

ABSTRACT:
High density VMOSFET devices, particularly single transistor memory cells, are provided by use of a series of simplified self-aligning process steps. Gate electrodes, source/drain regions and source/drain contacts are provided with the aid of an initial mask-less photoresist removal process in which a relatively thick layer of self-leveling photoresist is uniformly removed in order to define portions of a gate electrode within the recess of a V-groove. The gate electrode subsequently acts as a self-aligned mask to define implanted source/drain regions also within the V-groove and to enable second level interconnecting metallurgy contacts to be formed along the sidewalls of the V-groove.

REFERENCES:
patent: 3975221 (1976-08-01), Rodgers
patent: 4105475 (1978-08-01), Jenne
patent: 4225879 (1980-09-01), Vinson
patent: 4250519 (1981-02-01), Mogi
patent: 4316203 (1982-02-01), Tohgei

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