Apparatus for self-testing a digital logic circuit

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371 27, G01R 3128

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047792736

ABSTRACT:
A method is disclosed that lends itself to efficient incorporation in digital logic networks to enable such networks to automatically test themselves in place. A register is incorporated in the network in such a manner that a data pattern loaded in the register may be input to the network and the resultant outputs of the network may be captured in the same register. The resultant pattern may then be modified and the process repeated a number of times, after which the final pattern is compared with an expected one to verify correct operation of the network.

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Williams, T. W. "Design for Testability-A Survey", IEEE Transactions on Computers, vol. 31, No. 1, 1/82.

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