MOS no-leak circuit

Details MOS no-leak circuit MOS no-leak circuit

1987-04-08

1989-04-25

Miller, Stanley D.

Electrical transmission or interconnection systems

Nonlinear reactor systems

Parametrons

307443, 307475, 307585, H03K 19017, H03K 3037, H03K 19094

Patent

active

048251062

ABSTRACT:
A CMOS inverter circuit is coupled to a power source by a cut-off circuit which prevents current flow through the CMOS inverter circuit when the input signal to the CMOS inverter is of a first bi-level state. The cut-off circuit responds to the output signal from a second inverter circuit that is connected to receive the output of the CMOS inverter circuit. A second embodiment of the invention provides a latching function by connecting a feedback path from the output of the second inverter circuit to a toggle gate circuit connected to the input to said CMOS inverter circuit.

REFERENCES:
patent: 3914702 (1975-10-01), Gehweiler
patent: 4469959 (1984-09-01), Luke et al.
patent: 4518873 (1985-05-01), Suzuki et al.
patent: 4555642 (1985-11-01), Morales
patent: 4567385 (1986-01-01), Falater et al.
patent: 4584491 (1986-04-01), Ulmer
patent: 4593212 (1986-06-01), Svager
patent: 4633107 (1986-12-01), Norsworthy
patent: 4675544 (1987-06-01), Schrenk

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