Digital shift register using random access memory

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G06F 1531

Patent

active

051538466

ABSTRACT:
A tapped digital shift register suitable for use with a finite-impulse-response (FIR) filter in applications such as high-definition television is implemented using a random-access memory (RAM). The RAM contains x words having yz bits each, where x represents the number of elements in each section of the shift register, y represents the number of taps and z represents the number of bits in each element. Words are continuously read from and written back into the RAM. Before being written back, each word is modified by removing a z-bit portion from one end and appending a z-bit portion representing new information to the other end. The shift-register architecture disclosed is particularly suited for implementation on very-large-scale integrated circuits together with the FIR filter circuits.

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patent: 4777612 (1988-10-01), Tomimitsu
patent: 4791596 (1988-12-01), Harbich
patent: 5047972 (1991-09-01), Wada

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