Noise immunity in input buffer circuit for semiconductor memory

Details Noise immunity in input buffer circuit for semiconductor memory Noise immunity in input buffer circuit for semiconductor memory

1978-10-20

1981-09-08

Miller, Jr., Stanley D.

Electrical transmission or interconnection systems

Nonlinear reactor systems

Parametrons

307279, 307296A, 307DIG3, H03K 1760

Patent

active

042887062

ABSTRACT:
A random access read/write MOS memory device employs bistable latch or buffer circuits as the address inputs, data inputs, and the like. The buffers function to latch the data or address to allow the inputs to change states. The buffer is activated by TTL level inputs, exhibits low capacitance at its input, and switches states fast enough to allow rapid multiplexing of the addresses. Noise immunity is improved by selective implants of some of the transistors, and by use of filter capacitors connected between input nodes and Vss rather than Vdd.

REFERENCES:
patent: 4011639 (1978-08-01), Redwine
patent: 4031415 (1977-06-01), Redwine et al.
patent: 4081701 (1978-03-01), White, Jr. et al.
patent: 4181865 (1980-01-01), Kohyama

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