Field effect transistor

Details Field effect transistor Field effect transistor

1991-03-22

1992-10-06

Davie, James W.

H01L 2714

Patent

active

051536838

ABSTRACT:
A field effect transistor having an asymmetric gate includes high dopant concentration source and drain regions. The drain region is shallower and of lower dopant concentration than the source region. The drain is spaced from the gate electrode. Therefore, an ideal FET having a reduced short channel effect and having a lower source resistance and high current drivability (gm) is obtained. When the drain region is produced by ion implantation through a film and the source region is produced by the implantation directly into the substrate, only the drain region is separated from the gate. When the insulating film on the source region is separated from the insulating film on the drain region, the insulating film on the source region is reliably selectively removed, whereby high controllability is obtained.

REFERENCES:
patent: 4318216 (1982-03-01), Hsu
S. N. Chakravarti et al, "Double-Diffused Metal-Oxide Silion FET", IBM Technical Disclosure Bulletin, vol. 19, No. 4, Sep. 1976, pp. 1162-1163.
Geissberger et al, "A New Refractory . . . MMIC's", IEEE Transactions on Electron Devices, vol. 35, No. 5, 1988, pp. 615-622.
Enoki et al "Optimization of GaAs . . . MMIC", NTT Electrical Communications Laboratories, ED86-0, pp. 23-28.

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