1990-12-17
1992-01-21
Wojciechowicz, Edward J.
357 237, 357 235, 357 2314, 357 4, H01L 2702
Patent
active
050831909
ABSTRACT:
A stacked shared-gate CMOS transistor and method of fabrication are disclosed. An improved CMOS transistor is fabricated by the formation of a bulk transistor and an overlying isolated (SOI) transistor wherein each transistor is adjoined to a portion of a shared gate having the same conductivity type as the related transistor. The differential conductivity of the shared gate is obtained by the fabrication of a conductive diffusion-barrier layer intermediate to conductive layers. Improved switching performance is obtained as a result of higher current levels produced by the isolated transistor.
REFERENCES:
patent: 4982250 (1991-01-01), Manos et al.
Dockrey Jasper W.
Motorola Inc.
Wojciechowicz Edward J.
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