Reduced test time finite impulse response digital filter

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36472416, G06F 1710

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active

057904391

ABSTRACT:
A k-bit data input and a 1-bit scan input of a scan flip-flop (21.sub.i) of a multiply-accumulation operation unit (4.sub.i) respectively receive a k-bit data output and a 1-bit scan output of a scan flip-flop (21.sub.i-1) of a multiply-accumulation operation unit (4.sub.j-1) in the previous stage. A j-bit data input and a 1-bit scan input of a scan flip-flop (22.sub.i) respectively receive a j-bit data output of an adder (3.sub.i-1) of a multiply-accumulation operation unit (4.sub.i-1)) in the previous stage and a 1-bit scan output of a scan flip-flop (22.sub.j+1) in the next stage.

REFERENCES:
patent: 5339264 (1994-08-01), Said et al.
patent: 5487023 (1996-01-01), Seckora

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