System and method for using a frame buffer in cached mode to inc

Details System and method for using a frame buffer in cached mode to inc System and method for using a frame buffer in cached mode to inc

1995-10-05

1998-08-04

Swann, Tod R.

Computer graphics processing and selective visual display system

Computer graphic processing system

Plural graphics processors

711113, G06F 1200

Patent

active

057901376

ABSTRACT:
A system and method for increasing utilization of a system bus and frame buffer throughput in a graphic display system. The frame buffer is changed from cache inhibited mode to cached mode in order to take advantage of the burst mode of system bus in which a plurality of values are transferred to the frame buffer following one address. Data coherency is maintained between the cache and the frame buffer by invalidating a cache-line before writing to the cache-line, and by explicitly flushing the cache-line after the cache-line is filled with data.

REFERENCES:
patent: 5471592 (1995-11-01), Gove et al.
patent: 5493644 (1996-02-01), Thayer et al.
patent: 5493646 (1996-02-01), Guttag et al.
patent: 5522083 (1996-05-01), Gove et al.
patent: 5524265 (1996-06-01), Balmer

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