Method for controlling memory address of digital signal processo

Details Method for controlling memory address of digital signal processo Method for controlling memory address of digital signal processo

1997-12-31

1999-10-05

Nelms, David

Static information storage and retrieval

Addressing

365231, G11C 800

Patent

active

059634987

ABSTRACT:
Disclosed is a method for controlling a memory address of a digital signal processor in which a memory address is independently managed for each for during parallel processing of a plurality of jobs and no program of the same content as others is stored redundantly. Two bits of a high order A19 and A18 are masked among memory addresses of 20 bits from A0 to A19 which can be accessed for internal and external memories by a digital signal processor. In an address setting and an address computation performed on a program for executing each of jobs of the digital signal processor, only an address space of 18 bits from A0 to A17 can be accessed by an address pointer. The masked two bits of A19 and A18 are accessed by an address area register.

REFERENCES:
patent: 5206940 (1993-04-01), Murakami et al.
patent: 5771394 (1998-06-01), Asghar et al.

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