Excavating
Patent
1981-12-20
1984-08-14
Smith, Jerry
Excavating
371 37, 375116, 375110, 375114, G06F 1110
Patent
active
044660995
DESCRIPTION:
BRIEF SUMMARY
BACKGROUND OF THE INVENTION
1. Field of the Invention
This invention relates to information processing systems which utilize error correcting codes and which can benefit from the use of certain control signals. More particularly, the invention relates to incorporating special flag and/or status indicating code signals at random positions in serially ordered data without utilizing bit combinations which might otherwise normally be used to represent valid data.
2. Prior Art
There can be many situations in which it becomes desirable to include "flags" in fields of data that are utilized by an information processing system. These fields may be contained in a storage medium associated with the information processing system, or may be transmitted to the system via some communication link. For example, such flags could be used to provide synchronization of various kinds, to define the limits of variable length data messages, and to indicate the limits of storage fields assigned to various users in a multiprogramming system.
The typical straightforward approach to filling such a need is to allocate a particular combination of data bits to represent the desired flag. The disadvantage of this approach is that the number of bit combinations which can represent valid data are reduced if some of those combinations must be utilized to represent control flags.
Another approach to the problem is exemplified by U.S. Pat. No. 3,913,068 which describes a system in which data employed for synchronization purposes is arranged in a different code than data which represents information. With the instant invention, special symbols (flags) are coded in the same form as other data thereby conserving code utilization and bandwidth, as well as simplifying the system.
Other prior art of particular interest includes U.S. Pat. No. 3,836,957 and two articles appearing in the IBM Technical Disclosure Bulletin, Vol. 20, No. 9, Feb. 1978, pages 3579-3580 and 3585-3586. These items of prior art are of interest because they deal with responses by a system to syndromes which indicate the presence of a data error. However, they do not suggest utilizing error syndromes for purposes other than error handling. One manner in which the instant invention distinguishes significantly over such prior art is in utilization of predetermined data configurations and error syndromes for special system control.
BRIEF DESCRIPTION OF THE INVENTION
In accordance with a preferred embodiment of the invention, special characters are represented by predetermined combinations of data bits and error correcting code (ECC) redundancy bits. These predetermined combinations are selected from among the combinations which normally occur only when an uncorrectable error has occurred in a word. These predetermined patterns are decoded by the system as the special characters or flags. In the preferred embodiment, when a flag is recognized, no error indication will be transmitted to the using system.
The primary commercial advantages achieved with this invention are: the information system (because the combinations utilized for the flags would otherwise have no valid meaning); capability of the system; and
BRIEF DESCRIPTION OF THE DRAWINGS
FIG. 1 is a simplified block diagram of the invention as it would be incorporated into a typical information handling system.
FIG. 2 provides more details of an embodiment of the invention which can be used to detect a single special character.
FIG. 3 is an alternative embodiment of the invention similar to the one shown in FIG. 2, but which allows the determination of a multiplicity of different special characters within the same computer system.
DETAILED DESCRIPTION
The following descriptions of embodiments of the invention show how it can be incorporated into a typical information handling system. Aspects of such systems such as, for example, single error correction and specific detailed timing considerations, upon which this invention has little or no impact are not described in detail below. Those aspects will vary from system
REFERENCES:
patent: 3733585 (1973-05-01), Merlo
patent: 3836957 (1974-09-01), Duke et al.
patent: 3860907 (1975-01-01), Marshall
patent: 3913068 (1975-10-01), Patel
Chen, C. L. et al. "Error Migration Protection for Multiprocessor with Hierarchical Memory", IBM Technical Disclosure Bulletin, vol. 20, No. 9, Feb. 1978, 3579-3580.
Annunizata, E. J. et al. "Cache Error Handling in a Store-in-Cache Design", IBM Technical Disclosure Bulletin, vol. 20, No. 9, Feb. 1978, 3585-3586.
Galpin, R. J., Digital Synchronizer, Jun. 1972, IBM Technical Disclosure Bulletin, vol. 15, No. 1, pp. 81-83.
International Business Machines Corp.
Jablon Clark A.
Murray James E.
Smith Jerry
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