Low skew clocking system for VLSI integrated circuits

Details Low skew clocking system for VLSI integrated circuits Low skew clocking system for VLSI integrated circuits

1990-11-21

1992-11-17

LaRoche, Eugene R.

Electrical transmission or interconnection systems

Nonlinear reactor systems

Parametrons

307445, 307468, 307481, H03K 1900

Patent

active

051646196

ABSTRACT:
A low skew clocking system for VLSI intergrated circuits in which a reference chip, preferably a microprocessor, generates local synchronization signals for the other chips on a common PC board. This reduces the clock skew between the reference chip and all other chips by as much as 50%. Skew between chips is further reduced by using a differential MOS driver responsive to locally generated synchronization signals to generate differential synchronization outputs. Processing speed may be further improved in accordance with the invention by implementing a quadrature clocking scheme using the differential synchronization outputs from the MOS driver whereby the timing delays between the differential quadrature clocking signals are determined by the PC board delays. Also, by breaking the logic circuitry up into pipelined elements having propagation delays on average on the order of 1/4 of the system clocking period and applying the quadrature clock-scheme to interspersed latches, data may theoretically propogate through the logic and never be delayed by a clock edge. The system of the invention thus allows very high clock rates to be attainable for a given technology.

REFERENCES:
patent: 4761567 (1988-08-01), Walters, Jr.
patent: 5055707 (1991-10-01), Beard
patent: 5057701 (1991-10-01), Miller, Jr.
Jonathan Lotz et al., "A CMOS RISC CPU Designed for Sustained High Performance on Large Applications", IEEE Journal of Solid-State Circuits, vol. 25, No. 5, Oct. 1990, pp. 1190-1198.

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