Device comprising circuits for holding, in particular, a test da

Details Device comprising circuits for holding, in particular, a test da Device comprising circuits for holding, in particular, a test da

1979-03-13

1980-09-30

Atkinson, Charles E.

Excavating

324 73R, G01R 3128, G06F 1100

Patent

active

042259584

ABSTRACT:
An electronic device, such as an LSI, comprising a logic circuit and an electronic circuit that comprises, in turn, a large-capacity memory circuit and/or at least one oscillator is provided with a holding circuit between the logic and the electronic circuits and between the electronic circuit and a device output terminal. The holding circuit merely delivers output signals of the logic circuit to the electronic circuit and feeds back output signals of the electronic circuit to the logic circuit in normal operation of the device. During test of the logic and the electronic circuits, the holding circuit selects and holds a test signal of a preselected time-sequential pattern and is switched to select the logic circuit output signals, which are produced by the device with a prescribed combination of logic levels when the device has no defects. Similarly, a holding circuit output signal is given a predetermined time-sequential pattern. Preferably, the holding circuit comprises first and second holding circuits equal in number to inputs and outputs, respectively, of the electronic circuit to serve as mere data buses and a shift register in the normal and the test modes of operation, respectively.

REFERENCES:
patent: 3761695 (1973-09-01), Eichelberger
patent: 3789205 (1974-01-01), James
patent: 3961254 (1976-06-01), Cavaliere et al.
patent: 4038648 (1977-07-01), Chesley
patent: 4063080 (1977-12-01), Eichelberger et al.
patent: 4074851 (1978-02-01), Eichelberger et al.
Tsui, Arrangement for Minimized Functional Test of LSI Logic Chips, IBM Technical Disclosure Bulletin, vol. 15, No. 9, Feb. 1973, pp. 2870-2872.
Goel and Hsieh, Testing of Random Logic, IBM Technical Disclosure Bulletin, vol. 16, No. 2, Jul. 1973, pp. 429-430.
Leininger, On-Chip Testing Enhancement of a Single-Chip Microprocessor, IBM Technical Disclosure Bulletin, vol. 21, No. 1, Jun. 1978, pp. 5-6.

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