Pipelined cache system using back up address registers for provi

Details Pipelined cache system using back up address registers for provi Pipelined cache system using back up address registers for provi

1987-07-15

1990-02-13

Zache, Raulfe B.

Boots, shoes, and leggings

3642318, 364265, 3642663, G06F 938, G06F 1336, G06F 1114

Patent

active

049012282

ABSTRACT:
A cache memory includes an address back-up register for storing the physical address of the data where errors are generated for backing up the address register, a data array address back-up register for storing data address of the data where errors are generated for backing up the data array address register, and a request code back-up register for storing a preceding request code at the time of the error generation. When an error is detected by the system controller, data is read from the main memory according to the back-up registers and the control register, EYCY register and PSEDO ACK register, of the system controller.

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