Scan testable integrated circuit

Details Scan testable integrated circuit Scan testable integrated circuit

1982-09-09

1985-01-08

Smith, Jerry

Excavating

324 73AT, G01R 3128, G06F 1100

Patent

active

044930771

ABSTRACT:
A large scale sequential integrated circuit is made amenable to scan design testing by the inclusion of special multiplexing and storage circuits which respond to a pair of test control pulses to reconfigure the circuit to include one or more shift registers and to step the scan test data through the shift registers. In particular, the pair of test control pulses are applied to the two terminals to which, in normal operation, are applied the clock pulses which are used to control the storage elements and which, in such operation, are never both simultaneously high. To initiate the scan test operation, these test control pulses are made simultaneously high and the circuitry responds to such conditions.

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Goel et al., Functionally Independent AC Test for Multi-Chip Packages, IBM Technical Disclosure Bulletin, vol. 25, No. 5, 10/82, p. 2308.
Moser, LSSD Scan Path Truncated to Minimum Length for Testing, IBM Technical Disclosure Bulletin, vol. 25, No. 12, 5/83, p. 6547.
NEC Research & Development, No. 54, Jul. 1979, "Easily Testable Design of Large Digital Circuits," pp. 49-55.
Proceedings of the 1980 IEEE Test Conference, Paper 2.2, "Application of Shift Register Approach and Its Effective Implementation," pp. 22-25.
Proceedings of 14th Design Automation Conference, Jun. 1977, "A Logic Design Structure for LSI Testability," pp. 462-468.

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