Sequential prefetching with deconfirmation

Details Sequential prefetching with deconfirmation Sequential prefetching with deconfirmation

1990-01-05

1990-12-25

Fleming, Michael R.

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364900, 3642434, 3642631, 36424341, 36424612, 36424613, 3649642, 364948, G06F 1202, G06F 1300

Patent

active

049808230

ABSTRACT:
A computer memory management method for cache memory uses a deconfirmation technique to provide a simple sequential prefetching algorithm. Access sequentially is predicted based on simple histories. Each memory line in cache memory is associated with a bit in an S-vector, which is called the S-bit for the line. When the S-bit is on, sequentiality is predicted meaning that the sequentially next line is regarded as a good candidate for prefetching, if that line is not already in the cache memory. The key to the operation of the memory management method is the manipulation (turning on and off) the S-bits.

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"Simple Prefetching Scheme for Memory Hierarchy", IBM Technical Disclosure Bulletin, vol. 26, No. 1, Jun. 1983. pp. 52-54.
"Confirmed Prefetching with Confirmation on Exit", IBM Technical Disclosure Bulletin, vol. 29, No. 2, Jul. 1986, p. 911.
"Prefetch Confirmation/Access Array", IBM Technical Disclosure Bulletin, vol. 29, No. 3, Aug. 1986, p. 1380.

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