Process for making polysilicon field plate with improved suppres

Details Process for making polysilicon field plate with improved suppres Process for making polysilicon field plate with improved suppres

1987-12-21

1990-02-13

Hearn, Brian E.

Fishing, trapping, and vermin destroying

437 79, 437 53, 437 47, 437 50, 357 53, H01L 21316

Patent

active

049006932

ABSTRACT:
A method of forming silicon integrated circuits offers radiation resistance together with a high degree of planarity, including a thin field oxide together with a set of conductive plates over the field region combine to suppress the formation of parasitic transistors. In one embodiment, a silicon substrate is etched to form trenches and is then covered with a thin barrier layer, (410) of high quality thermal oxide. A polysilicon layer (423) is next conformally deposited and planarized until the barrier layer (410) is exposed, followed by an oxidation step for isolation or gate oxide formation.

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Sze, S. M., VLSI Technology, McGraw-Hill, 1983, pp. 140-157.
Ghandhi, S. K., VLSI Fabrication Principles, John Wiley & Sons, 1983, pp. 376-401.

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